Yes, you can. Yes, people do. But there are a couple
of things to watch out for. One is, the ramp time through
the linear window of the front end (that is, in the second
chart from ata_sa16, the region where the ouputs show
any non-flat-line quality, plus some) must be much less
than the delay time through the amplifier or you will
pick up an error term that roughly is dV/dt*prop_delay
and looks like Vio (but will flip sign if you flip ramp).
The other issue is, TRAN analysis error tolerances are
usually much looser than DC / OP tolerances and a
tiny bit of error residue at one spot in the amplifier
can make a big difference at another. Cranking down
the TRAN error tolerances will really blow out solution
time.
That said, TRAN is always a good thing to look at,
because it can expose other issues of behavior. Not
necessarily the most "accurate" simulation but often
a more realistic simulation of how the part works in
reality.