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offset cancellation/correction circuit for opamps

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pankaj jha

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Hello everyone,

I designed an opmap in schematic view in Cadence. It is giving no offset.
Then I did the layout for the same, and I get an offset of ~20mV between the differential output nodes.
Can anyone suggest me the way to do away with it? Or is there any circuit which when augmented with the present circuit cancels the offset.??
Any paper/book/reference is welcome...
 

kemiyun

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First of all, it's not "not giving an offset". It definitely has an offset voltage but since your simulations are run with perfectly matched devices you're just not seeing it. Run monte carlo and then start stressing about the offset. Also even if your devices are perfectly matched you'd still see a very small offset which is the effect of finite gain of the amplifier.

My best guess is that since this is a fully differential amp, you have some kind of asymmetry in your layout causing this. It is interesting as I wouldn't think it would affect the DC performance this much, but I'm not sure. But anyway 20mV offset without any imperfections is still too much. So before going into augmenting it first make sure this is working at its best.

For augmentations, there are lots of things you can do, simplest is just trimming it. But you need to be able to measure it and correct it, which is not a very easy thing. Also you can try chopper kind of stuff. There are devices with offsets as low as uVs using this kind of architecture.
 

pankaj jha

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First of all, it's not "not giving an offset". It definitely has an offset voltage but since your simulations are run with perfectly matched devices you're just not seeing it. Run monte carlo and then start stressing about the offset. Also even if your devices are perfectly matched you'd still see a very small offset which is the effect of finite gain of the amplifier.

My best guess is that since this is a fully differential amp, you have some kind of asymmetry in your layout causing this. It is interesting as I wouldn't think it would affect the DC performance this much, but I'm not sure. But anyway 20mV offset without any imperfections is still too much. So before going into augmenting it first make sure this is working at its best.

For augmentations, there are lots of things you can do, simplest is just trimming it. But you need to be able to measure it and correct it, which is not a very easy thing. Also you can try chopper kind of stuff. There are devices with offsets as low as uVs using this kind of architecture.

Thanks Kemiyun... Actually I have designed a low power opamp, where the total dc current consumption is ~100nA (with 1.8V supply). Is the dc offset problem more pronounced for low power designs??
 

dick_freebird

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One useful question is, does the schematic-based simulation
differ from its matched-layout (extracted) based results? Or
are these perhaps separated in time and maybe a few "minor"
value or topology differences?

Trimming requires that your devices be very stable vs aging
and environment. Chopping / autozero requires that you are
able to tolerate an output filter and/or have a period in which
the zeroing can be done. You need to explore these issues to
select an approach which won't make trouble for the application.
 

Warpspeed

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Check out the datasheet of the intersil ICL7650 chopper amplifier chip.
https://datasheets.maximintegrated.com/en/ds/ICL7650-ICL7650B.pdf

This is a chopper stabilized op amp that has internal circuitry that constantly corrects for input offset, and corrects it.
These are brilliant for current shunts and thermocouples, and making similar very low voltage dc measurements.
 

jiripolivka

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Most opamps have some drift, also it is variable by temperature. Chopped opamps are the best solution, some are costly.
Texas Instruments designed TLC 4502 with "digital drift compensation" before 2000, it may be a low-cost device now.
 

kemiyun

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Thanks Kemiyun... Actually I have designed a low power opamp, where the total dc current consumption is ~100nA (with 1.8V supply). Is the dc offset problem more pronounced for low power designs??
Of course, 100 nA implies that you have very small overdrive voltage on your devices and the devices themselves are very small. Both are things you need to avoid if you are going for low offset. Even 1 mV threshold shift would kill in this case and the expected distribution is given in terms of gate area in your process documents. Although I don't think it would make so much difference for the input devices since these usually are in deep threshold anyway. But I don't know your topology so I'm just speculating.

But remembering you said you didn't have this offset at schematic level, I'm still thinking debugging needs to be done at layout level before going into improvements by other means. Because 20 mV is a bit excessive after layout, assuming it's only coming from layout. Check for the device currents in your extracted simulation, there has to be something drastically different from your schematic. And since you have so low current it doesn't have to be absolutely large difference, a few nano amps would do it.

The reason I'm still thinking this way is because except for standalone amplifiers or extreme precision amplifiers in analog systems not every amplifier gets a special treatment. People usually get rid of its effects in firmware and stuff, because offset and its drift is actually an inherent problem and costly to solve at hardware level for each and every amplifier there is in the system. So you should be able to get 5-10 mV offset in monte carlo and almost zero from perfectly matched circuit and usually that would be good enough for most cases. If not then go for improvement, but even then not for every amplifier in your system.

If you are still willing to go for improvements by other means, other people have given good advice, weigh its costs and go for it :D And one thing I haven't considered is that you may be doing this as a practice, then definitely go for it.
 

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