levnu
Full Member level 2
Question: What are the layout guidelines that will allow me to minimize the Y1 mil & Y2 mil sizes (see attached picture) such that the below 10MHz OCXO frequency stability will not have a performance degradation?
Do I have to place the GND between the OCXO out to Vc etc. or maybe I can remove it?
What is the required distance between OCXO out and GND? can it be minimal as PCB manufacture allows?
Do I have to place the GND between the OCXO out to Vc etc. or maybe I can remove it?
What is the required distance between OCXO out and GND? can it be minimal as PCB manufacture allows?