[SOLVED] Novice and Silly Questions about FPGA (1- Not technical, 2- Macro 3- Clock )

[stark43]

Hello everyone ,
1) In the FPGA world, there is the concept of IP and when I use these IPs, I cannot feel myself as a designer (What I am talking about is not ASIC). Is this feeling wrong? In the business world, do people write the design themselves or do they use IPs?
2) For example, we need an I2C hardware. FPGAs also have embedded I2C (I think it's called macro) blocks. What is the advantage of using these blocks? (Maybe speed, else?)
3) Slower protocols also clock at low speed. What is the best way to create these clocks? I guess clock dividers aren't very welcome in the FPGA world. Is it more accurate to produce with PLL? But on the one hand, wouldn't we have a CDC problem because we defined a different time field?

 

[kaz1]

If you don't want use ip then why also not use the compiler or manufacture own fpga or start from foundry making silicon wafers or better design the foundry itself. It is chain of work and you want to be part of it based on speed/cost ...etc

 

[dpaul]

1. Depends on what is being designed. No one wants to spend time in designing and verifying a module/IP which is obtained for free/very low price.
The straight way of thinking is - if there is an IP core which provides the functionality you want to implement (and which also uses reasonable silicon area), then just use it. Else write your own module/IP.

2. Which FPGA has an embedded I2C? I know of none! FPGA vendors might provide I2C Master IP cores but it cannot be called a macro/primitive.
Macros are not IP cores. Macros are FPGA vendor specific components such as IO Buffers, clock buffers, multipliers, PLLs, DPLL, BUFGMUX, Etc which can be directly instantiated in your RTL.

3. You have the MMCM/PLL macro.

 

[FvM]

1. We write FPGA code to solve application problems, not to feel as a designer. Utilisation of existing IP is a pragmatic choice, how to achieve the design goals in time and at acceptable costs. There are different flavours of IP. Vendor IP, partly provided for free, for optimal support of specific FPGA features. We'll use it where ever possible, sometimes with modifications. And paid third party IP. Not cheap but most likely cheaper than writing it yourself.
2. There are a very few FPGA with dedicated SPI or I2C functionality, e.g. Lattice MachXO2 series
3. Slow peripherals are mostly operated in the main clock domain using divided clock enable signals.