Tajwar
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Can any1 help me . y im not getting shifted clock at output?
here is the code for it
module test(input clk, rst, inc,ref_clk, enable, output reg s_clk1, s_clk2, output done, clk_valid
);
wire temp1, temp2;
always@(posedge ref_clk)
begin
if(rst)
begin
s_clk1<=0;
s_clk2<=0;
end
else
begin
s_clk1<=temp1;
s_clk2<=temp2;
end
end
dcm1 instance_name
(// Clock in ports
.CLK_IN1 (clk), // IN
// Clock out ports
.CLK_OUT1 (temp1), // OUT
.CLK_OUT2 (temp2), // OUT
// Dynamic phase shift ports
.PSCLK (ref_clk), // IN
.PSEN (enable), // IN
.PSINCDEC (inc), // IN
.PSDONE (done), // OUT
// Status and control signals
.RESET (rst), // IN
.CLK_VALID (clk_valid)); // OUT
// INST_TAG_END ------ End INSTANTIATION Template ---------
endmodule
here is the code for it
module test(input clk, rst, inc,ref_clk, enable, output reg s_clk1, s_clk2, output done, clk_valid
);
wire temp1, temp2;
always@(posedge ref_clk)
begin
if(rst)
begin
s_clk1<=0;
s_clk2<=0;
end
else
begin
s_clk1<=temp1;
s_clk2<=temp2;
end
end
dcm1 instance_name
(// Clock in ports
.CLK_IN1 (clk), // IN
// Clock out ports
.CLK_OUT1 (temp1), // OUT
.CLK_OUT2 (temp2), // OUT
// Dynamic phase shift ports
.PSCLK (ref_clk), // IN
.PSEN (enable), // IN
.PSINCDEC (inc), // IN
.PSDONE (done), // OUT
// Status and control signals
.RESET (rst), // IN
.CLK_VALID (clk_valid)); // OUT
// INST_TAG_END ------ End INSTANTIATION Template ---------
endmodule
