Noob's question about sensitivity list and timing of signals

Hello,

I am a total noob in VHDL/Verilog so I ll need your valuable help. I am trying to design a 2x2 ethernet switch like this : https://github.com/kc285/ethernet/tree/master/SystemVerilogReference/projects/ethernet

I have only one clock clk, and I want to have a syncrhonous start of packet A signal (in_sopA) so in the testbench i write


inside the design I have written


so i notice that write_en_A is asserted after 2 clock cycles and not during the current posedge of the clk. So I believe there is a problem tracing posedge of in_sopA because posedge of in_sopA is happening nearly the same time with if1.clk posedge. Should I add another clock and generate in_sopA with the second clock?

i tried changing the sensitivity list to


end it works fine.


2nd question ,

can you please guide me how would you try to design a 2x2 switch ? Your first thoughts of the overall architecture

3rd, can you give me some general guidelines of when one should use FSM in a design?


Thank you very much, I would kindly ask you, if you have the kindness to answer my questions to be as illustrative as you can.
Thank you again

I'm not a Verilog guy, but it looks to me like what you've actually done is changed your clock from if1.clk to in_sopA; not what I think you intended.

If you draw a timing diagram, that will help you understand why you've got a 2 clock delay. On the first clock, in_sopA changes. So, write_en_A won't change until the second clock.

But if you're a noob, I would think you might want a much simpler project than an Ethernet switch.

I'm not sure about your FSM question. I don't know if there are any 'rules', I kind of just use intuition (and experience). Certain processes just obviously lend themselves to FSMs. If things need to happen in a sequence, then an FSM is probably the right way to go. Draw a state-flow diagram.

Understand the code in your 'design' describes a flip flop with clk of if1.clk and a clock enable of (in_sopA == 1'b1 && full_A == 1'b0).

Given that, it assigns 1 to write_en_A on the first posedge where the clock enable is true. That's probably 1 clock cycle after your clock enable statement becomes true.

change your testbench, make it blocking and operate on the opposite clock edge of the design.

@op: sensitivity lists are almost never the answer. They are a legacy burden that are increasingly being marginalized. Synthesis mostly ignores it. For Verilog, synthesis uses it to determine the clock and (optional) async clear for a FF. Fixing sim issues by tweaking the sensitivity list might mean the sim works but the synthesis doesn't.
You should use "@(posedge clk or negedge aclr)", "@(posedge clk)", and "@(*)". In system verilog, you should use always_ff and always_comb. (sometimes you might have a negedge clk, or posedge aclr)

When you have always@(posedge clk) or always_ff, you should mentally think that you are writing logic for the next cycle. For an FSM, this means writing output logic based on transitions.
When you have always@(*) or always_comb, you should mentally think that you are writing logic for the current cycle, or that you are writing the next_value logic for a register and that this next_value logic could be used in the current cycle.

In Verilog/VHDL, a value is retained if nothing in the always block updates it. for always@(*), this means a value not assigned in all code paths infers a latch. always_comb can detect this.