no synthesis error and timing constraints are met.
i ll upload the code below:
in this code, the period of CLK is 20ns and demod_clk is 1320ns
TX_DATA and RX_DATA are set of 24 data points which are 32767,40609,47995,54496,59735,63406,65296,63406,59735,54496,47995,40609,32767,24924,17538,11037,5798,2129,238,2129,5798,11037,
17538,24924
TX_DATA is the refference wave and RX_DATA is the incoming wave. i am using same numbers for both for the sake of verification.
Code:
entity scheme_demod is
Port ( TX_DATA : in signed(16 downto 0);
RX_DATA : in signed(16 downto 0);
clk : in std_logic;
demod_clk : in STD_LOGIC;
--rx_data_compl : in std_logic;
tx_data_compl : in std_logic;
b_count : out std_logic;
start_data : out std_logic;
start_data1 : out STD_LOGIC;
DATA_OUT : out std_logic_vector (39 downto 0)
);
end scheme_demod;
architecture Behavioral of scheme_demod is
type bus_type is array(0 to 23) of integer range 0 to 65535;
type bus_type1 is array (0 to 23) of signed (16 downto 0);
signal temp_rx : bus_type1 :=(others =>(others => '0'));
signal temp_tx : bus_type1 :=(others =>(others => '0'));
signal newrx : bus_type1 :=(others =>(others => '0'));
signal i,p : integer :=0;
signal moore_rx : signed (16 downto 0);
signal new_rx : signed (16 downto 0);
signal dif : signed (16 downto 0);
signal temp_sum : signed(39 downto 0) :="0000000000000000000000000000000000000000";
signal a,b : std_logic;
signal zc_clk,demod : std_logic;
signal test,test1 : std_logic := '1';
begin
start_data <= test;
start_data1 <= test1;
process(demod_clk,clk)
begin
if rising_edge(demod_clk) then
test <= '1';
temp_tx(i) <= TX_DATA - 32767;
temp_rx(i) <= RX_DATA - 16384;
moore_rx <= temp_rx(i);
i <= i + 1;
end if;
if rising_edge(clk) then
dif <= 0 - moore_rx;
if (0 - moore_rx > 0) then
a <= '0';
else a <= '1';
end if;
end if;
if rising_edge (demod_clk) then
b <= a;
end if;
if i = 24 then i <= 0; end if;
end process;
zc_clk <= (not b) and a;
process(zc_clk,demod_clk)
variable k : integer:=0;
begin
if zc_clk' event and zc_clk = '1' then
demod <= '1';
k := 1;
end if;
if falling_edge(demod_clk) then
if demod = '1' then
-- b_count <= '0';
newrx(k) <= moore_rx;
new_rx <= newrx(k);
temp_sum <= temp_sum + newrx(p) * temp_tx (p);
p <= p + 1;
k := k+1;
end if;
end if;
if k = 24 then
k :=0;
end if;
if rising_edge (demod_clk) then
b_count <= '0';
if p = 24 then
b_count <= '1';
DATA_OUT <= std_logic_vector(temp_sum);
temp_sum <= "0000000000000000000000000000000000000000";
p <= 0;
end if;
end if;
end process;
end Behavioral;