let me guess the answer for those characteristics below
when the input value is very small i,e less than volt equivalent temperature the circuit will not respond to it,
then the voltage generated at the output terminals at room temperature will be observed at output terminals.
(sorry if i am wrong)
Yes. At least it doesn't show the exact circuit behaviour. To get an idea about it, you can assume different loads, e.g. capacitive or resistive, both pull-down and pull-up and consider the expectable output with 0 -> Vdd -> 0 triangle input waveform.
Thank you, everyone.
Could you tell me how to derive Vout = Vt as Vin < Vt?
As Vin < Vt, which operating region each mosfet is?
I think pmos will be ON and NMOS will be in sub-threshold region.
Ok . Then sketch the output characteristics (log. Ids vs. Vds, parameter Vgs) of the 2 FETs. The NMOS sources, the PMOS sinks this current. For approximation take their saturation currents, e.g. @ Vds=Vdd/2, with these calculate their DC output resistance Rout = Vds/Ids (again Vds=Vdd/2), then consider these 2 Rout's as voltage divider - so get your Vout.
Of course this is an approximation, but it works because the Ids changes from Vgs < 0 (OFF) via Vgs=0 to Vgs=Vth (sub-threshold) to Vgs > Vth (ON) - and so the Rds changes - are relatively steep.