Non-idealities of current mode loop gain model - questions

[kanmaedexandzelbladex]

Hello everyone, I've read this paper: https://u.dianyuan.com/bbs/u/39/1143802025.pdf about designing stable control loops for fixed frequency current mode controlled converters. In the pdf, at page 26 we see an approximate formula for the loop gain of a boost converter in fixed frequency current mode.

I just want to ask 2 questions:

1.) I've read from other sources that circuit delays could cause phase margin drops (Pade Approximation). I would like to ask how to incorporate it in the loop gain. I've read that the transfer function block modelling this would be, T = e^-st_d, which would be multiplied to the current loop gain to get the more accurate bode plot. But for the overall loop gain, I am not sure if it is as simple as multiplying the block. Another thing is how do I get the value of td? In my circuit I probably have mosfet switching delays, and my current mode comparator also has it. Also, my snubber circuit which suppresses Vds,spike would also cause the switching to be slower hence they give delays. My question is how do I extract the value of t_d? I mean, I know the rise times and fall times my Vds or Vgs waveform gets due to these delays but I do not know what is the t_d which I would use for the modelling.

2.) In the formula for the loop gain in the pdf, can I multiply (1+sRC) to the Rs factor since the model by which the formula was derived assumed that the current is passed through a sense resistor Rs which outputs a voltage which is directly fed to the current mode comparator. In my implmentation, I have an RC lowpass filter before I feed the signal into the comparator. I therefore will be adding a new pole in the model. Is this correct?

3.) Other models show there is a zero due to the output capacitor ESR. In the formula however it does not show any. It also doesn't seem to explain in the pdf what happened to the output ESR capacitor. Can you shed light on this?

Thanks!

 

[mtwieg]

I can't get the pdf to load completely, could you attach it in a post here?

The delay affects the loop transfer function of the inner current mode control loop, multiplying it be e^-st is correct. Then based on that its closed loop transfer function will be modified, and that can be used incorporated in the model of the full boost converter.

The delay time will consist of the delay in the pwm comparator, gate driver, and FET, but should not depend on any voltage snubbers.

 

[FvM]

As most SMPS models, the paper is using an continuous time equivalent circuit. In most cases, the average delay of the pulse width modulator is a major contribution to loop delay. It's a systematical rather than a non-ideality parameter.

3.) Other models show there is a zero due to the output capacitor ESR. In the formula however it does not show any. It also doesn't seem to explain in the pdf what happened to the output ESR capacitor. Can you shed light on this?

I don't understand the statement. ESR is considered in most design example of the paper. Did you read it completely?

 

[kanmaedexandzelbladex]

As most SMPS models, the paper is using an continuous time equivalent circuit. In most cases, the average delay of the pulse width modulator is a major contribution to loop delay. It's a systematical rather than a non-ideality parameter.



I don't understand the statement. ESR is considered in most design example of the paper. Did you read it completely?

Umm, well yes the paper takes into consideration the ESR of the output capacitor in the design like in page 28 where he based some of the values of the resistor and capacitor of the Type II compensator on the location of the ESR of the boost output capacitor. My question really is in the form of the loop gain. In page 26, the loop gain has an RHPZ and two poles multiplied by a DC gain and the compensator gain but it does not have the zero due to the output ESR. In this pdf https://www.ridleyengineering.com/images/current_mode_book/Current_Mode_Chapter_7.pdf however, in page 3 of 11, the boost converter current mode loop gain includes the output ESR. The model is slightly different in that it includes the high frequency correction term.

I would also like to ask about how significant can be the effect of the delay of the pulse width modulator? Can it reach to like phase margin drops of 20 degrees from calculations without considering it? Do you know how I could somehow change the loop gain transfer function to include this delay in the calculation? The comparator I am using for my current mode has a delay based on the datasheet so I think I have enough information to model it.

The reason I'm wondering about these stuff is because I have a fixed frequency current mode boost converter. My simulations in MATLAB of the transfer function based from the first pdf link I showed here shows very good phase margins and gain margins (about at least 78 deg PM and at least 15 dB GM for all input and loading conditions). My circuit simulation (complete circuit) in SIMetrix somewhat agreed with the math simulations since there is no ringing in the output voltage during start and the steady-state level is achieved at a long time. Applying input and load step changes also do not cause ringings. In the hardware implementation however I get pulse-skippings, like subharmonic oscillations. I am still in the process of understanding where it might have come.

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I can't get the pdf to load completely, could you attach it in a post here?

The delay affects the loop transfer function of the inner current mode control loop, multiplying it be e^-st is correct. Then based on that its closed loop transfer function will be modified, and that can be used incorporated in the model of the full boost converter.

The delay time will consist of the delay in the pwm comparator, gate driver, and FET, but should not depend on any voltage snubbers.

Here is the pdf.

Is there an easy way to incorporate the e^-st block in the overall loop gain? Like say I have the overall feedback loop gain of the boost converter. How do I attach the e^-st. Do I just multiply it?

 

[FvM]

ESR doesn't appear in the pg. 26 expression,so yes it's apparently ignored here.

Regarding PWM related delay, a rule of thumb for controllers based on average quantities is 1/2 of the switching period. It can easily make 20 degree additional phase shift. Yes, it's simply a multiplicative e^-st term, in other words a pure phase shift.

 

[kanmaedexandzelbladex]

ESR doesn't appear in the pg. 26 expression,so yes it's apparently ignored here.

Regarding PWM related delay, a rule of thumb for controllers based on average quantities is 1/2 of the switching period. It can easily make 20 degree additional phase shift. Yes, it's simply a multiplicative e^-st term, in other words a pure phase shift.

Thank you very much! I would just like to clarify that the e^-std term is to be multiplied with the overall outer loop gain and not just in the inner current loop? In other words, I can just multiply it with the equation in page 26 of the pdf of the loop gain? I would also like to clarify if the delay t_d is the cumulative sum of the propagation delay of the current mode comparator (pulse width modulator) and the turn-on delay of the mosfet?

Are there any other stuff in the circuit which might cause noticeable drops in PM and/or GM which I could look into?

 

[mtwieg]

Regarding PWM related delay, a rule of thumb for controllers based on average quantities is 1/2 of the switching period. It can easily make 20 degree additional phase shift.

1/2 of the switching period is really extreme, for low power DC-DC converters it should be well under 1us, never more than a tenth of the switching period.

Thank you very much! I would just like to clarify that the e^-std term is to be multiplied with the overall outer loop gain and not just in the inner current loop? In other words, I can just multiply it with the equation in page 26 of the pdf of the loop gain? I would also like to clarify if the delay t_d is the cumulative sum of the propagation delay of the current mode comparator (pulse width modulator) and the turn-on delay of the mosfet?

Strictly speaking I don't think it's correct, but it's probably a very close approximation.

Are there any other stuff in the circuit which might cause noticeable drops in PM and/or GM which I could look into?

If you really want to get into gory details:
1. Non-zero source impedance on the converter's input
2. Finite gbwp of the error amplifier
3. Analysis across your full line/load range (including any that might put you in discontinuous conduction)
4. Nonlinearities in inductors and capacitors (if you're using ferrite inductors or ceramic capacitors).

 

[FvM]

1/2 of the switching period is really extreme, for low power DC-DC converters it should be well under 1us, never more than a tenth of the switching period.

I'm talking about the systematical delay of the pulse width modulator. The PWM comparator senses the output voltage once per PWM period, thus an arbitrary disturbance will cause a reaction after averagely 1/2 PWM period.

 

[mtwieg]

I'm talking about the systematical delay of the pulse width modulator. The PWM comparator senses the output voltage once per PWM period, thus an arbitrary disturbance will cause a reaction after averagely 1/2 PWM period.

This is the case with regular sampling PWM, but for natural sampling PWM the phase response is very small (and can lead or lag, depending on specific conditions).

 

[FvM]

This is the case with regular sampling PWM, but for natural sampling PWM the phase response is very small (and can lead or lag, depending on specific conditions).

I don't think that the difference matters in this relation. The sampling time can be considered as fixed for a small signal disturbance, also with natural sampling.

You have reduced delay in control loops that evaluate the instantaneous rather than an averaged process value. This is the case for the inner current control loop of a current mode controller and the voltage control loop of special PWM controller topologies.

Usual pulse width modulators, e.g. the examples in the post #1 paper show however a 1/2 PWM period average delay.

 

[mtwieg]

I don't think that the difference matters in this relation. The sampling time can be considered as fixed for a small signal disturbance, also with natural sampling.

You have reduced delay in control loops that evaluate the instantaneous rather than an averaged process value. This is the case for the inner current control loop of a current mode controller and the voltage control loop of special PWM controller topologies.

Usual pulse width modulators, e.g. the examples in the post #1 paper show however a 1/2 PWM period average delay.

I've put time into simulating natural pwm modulation in matlab (for sinusoidal perturbations, and looking at the fundamental component of the pwm waveform's spectrum), and I just don't see it. And I definitely haven't seen it in any of my actual work building high frequency envelope tracking supplies (but I do see delays due to hardware limitations). If that amount of delay were there, then many of my results wouldn't be possible.

 

[FvM]

I should believe your results. I'm presently not sure under which circumstances I have seen the said modulator delay. May be it's regular sampling. I have to check some simulations, thanKs so far for insisting in this point.

 

[mtwieg]

Here's the matlab code I've been toying with, in case you're interested. For cases where the carrier and reference frequency aren't integer multiples of each other (and therefore the pwm is not periodic), increasing N_T1 is necessary for the results to converge towards reasonable values. Ultimately after manually playing around with the parameters I've never seen the lag become more than %15 of the PWM period.

There are some papers on the subject, but I haven't found one with the math explained thoroughly enough for me to follow it, unfortunately.

clear all
close all

fc=100e3;                   %frequency of pwm ramp
f1=20e3;                    %frequency of sinusoidal perturbation

R0=0.85;                    %normalized offset of perturbation, average duty cycle of PWM
R1=0.1;                     %amplitude of perturbation
ph1=pi/2;                   %initial phase of perturbation
phc=1*pi/2;                 %initial phase of pwm ramp (must be positive!)

dt=10e-9;                   %time step
N_T1=2;                    %number of reference periods to simulate
t_f=N_T1/f1-dt;             %final simulation time
t=[0:dt:t_f];               %generate time base


r=R0+R1*cos(2*pi*f1*t+ph1); %generate time-domain perturbation r
dc=fc*t_f/(t_f/dt);
C=[phc/(2*pi):dc:fc*t_f+phc/(2*pi)];            %generate time-domain ramp carrier
C=rem(C,1);
pwm=(r>C);                  %generate time-domain pwm

figure(1)
subplot(4,1,1)
plot(t,r)
title('Perturbation r')
xlabel('Time t')
subplot(4,1,2)
plot(t,C)
title('Carrier C')
xlabel('Time t')
subplot(4,1,3)
plot(t,pwm)
title('PWM output')
xlabel('Time t')

f_axis=[-1/(2*dt):1/(t_f+dt):1/(2*dt)-1/(t_f+dt)]; %create frequency axis for spectrum plots

r_spec=fftshift(fft(r));                            %fft of reference r
pwm_spec=fftshift(fft(pwm));                        %fft of pwm
r_ph=angle(r_spec(find(abs(f_axis-f1)<=10)));       %phase angle of reference
pwm_ph=angle(pwm_spec(find(abs(f_axis-f1)<=10)));   %phase angle of pwm fundamental
pwm_lag_ph=(pwm_ph-r_ph)                            %lag of pwm fundamental relative to r, in radians
pwm_lag_angle=pwm_lag_ph*180/pi                     %in degrees...
pwm_lag_time=-pwm_lag_ph/(2*pi)/f1                  %in seconds
pwm_lag_Tc_frac=pwm_lag_time*fc                     %as a fraction of carrier period

figure(2)
plot(f_axis,real(r_spec),f_axis,imag(r_spec),f_axis,abs(r_spec))
title('Spectrum of reference')

figure(3)
plot(f_axis,real(pwm_spec),f_axis,imag(pwm_spec),f_axis,abs(pwm_spec))
title('Spectrum of pwm')

pwm_spec_f1=pwm_spec.*((abs(f_axis-f1)<=10))+ pwm_spec.*((abs(f_axis+f1)<=10));

figure(4)
plot(f_axis,real(pwm_spec_f1),f_axis,imag(pwm_spec_f1),f_axis,abs(pwm_spec_f1))
title('Spectrum of pwm, fundamental component only')

pwm_f1=ifft(ifftshift(pwm_spec_f1));                %generate time-domain fundamental component of pwm
figure(1)
subplot(4,1,4)
plot(t,r,t,real(pwm_f1)+R0)
title('Fundamental component of reference and pwm')
xlabel('Time t')
legend('input r','fundamental of pwm')