I am wondering where ur physical and circuit came from?
I've achieved aproject that some non clock cell in the clock path, but It is a very slow project (clk period = 9ms), and there's no timing violation during STA.
Normally, we can not add non clock cell into the clk path during CTS, course backend tools do not allow to do so.
Non clock cells can not met the clkbufs' default setting, such as tinming, drive, load attributes.
Hi When you build the Clock tree you need to specify the cells or buffers to be used. Usually these CT cells are hidden and you need to unhide them for the tool to use. And no, you should not use these cells in the clock path. It will affect your clock tree robustness