noise margin of cmos inverter

[steven23]

In CMOS inverter, why VIH and VOL are defined at the slope of -1..why not less than -1.??

 

[srizbf]

In CMOS inverter, why VIH and VOL are defined at the slope of -1..why not less than -1.??

if it is defined at less than -1 , it means that the output will change drastically for a small input change.

a safe point is at slope=-1.

 

[steven23]

i am not convinced with this logic..my question is what if we define it at a slope of -0.8 value..is that acceptable value??
one answer comes to my mind is, by defining it at less than -1 will reduce the noise margins, which should be as large as possible( because VIL will decrease and VIH will increase)..and how do we define VOH and VOL??

 

[srizbf]

i am not convinced with this logic..my question is what if we define it at a slope of -0.8 value..is that acceptable value??
one answer comes to my mind is, by defining it at less than -1 will reduce the noise margins, which should be as large as possible( because VIL will decrease and VIH will increase)..and how do we define VOH and VOL??

at -0.8 it will reduce the margin. but the reduction in voltage will be safe value.
at -2 , then o/p can fall/rise steeply.

Voh is due to pullup and Vol is due to pulldown device .