Nodeset for subcircuit

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titanic

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Hi,

For cadence analog design envirenment i built 32x32 memory array. I want to nodeset the sram latch.

If i use simulation -> convergence aids -> nodeset , i am gonna have to nodeset every instance of the 6T memory cell.


How can i nodeset subcircuit so that , every instance obeys that nodeset arrangement ..?


(i.e. making nodeset as a property of 6T sram subcircuit for simulation by default)

thanx in advance
 

Should be possible with a hierarchical netlist.
 

It would be easy with hspice or spectre in text mode. But I could not figure out with analog environment and virtuoso ...
 

AFAIR hierarchical netlisting is also possible within Virtuoso's ADE. Usually, netlisting uses the foll. default rep- & stopList:
Code: 
  repList "spectre cmos_sch cmos.sch schematic veriloga ahdl"
  stopList "spectre veriloga"

So if your memory cell has a spectre view, the stopList makes sure to netlist the cell hierarchically, i.e. won't go deeper into the schematic.

Hope this works!
 

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