No timing violation still gate level simulation is failing

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shhrikant1

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Hi,

I have checked the timing reports and they are clean , yet when I do the gate level simulation with netlist and sdf , it is failing.
can anyone throw some light on this.
 

Difficult to say with only this much info.
Have you checked your synthesis report thoroughly?
 

shhrikant1 said:
Hi,

I have checked the timing reports and they are clean , yet when I do the gate level simulation with netlist and sdf , it is failing.
can anyone throw some light on this.
Click to expand...

Do all of the inputs to the DUT meet the timing requirements spelled out in the timing report (i.e. input XYZ is there Tsu ns before the rising edge of CLK)?

Kevin Jennings
 

And are those inputs held for Tco ns after the rising edge...
 

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