HI,
I am trying to connect 5 PMOS in parallel.It has the Vdd supply connected in the source side and two pins namely A and B at the gate and the drain.
I am not able to parse the DRC stage.It is showing an error named "No stamped connections".Could anyone anyone guide me in this.
I am attaching the screenshot of the same for the reference.
The reason why it does not able to parse your DRC stage because you don't have an ntap contact to be connected to Vdd supply and ptap contact(substrate contact) to be connected to your Gnd.
Hi,
Thanks for the replies.But I am just wondering what the name of the contact is.
Also one more thing.I have never used such contacts before for PMOS connection at substrate(I was designing both PMOS and NMOS as an inverter by then) and how come it can show the DRC error this time when I am trying to connect only PMOS's in parallel.
ntap contact -consist of the following layers (NWELL/NPLUS/ACTIVE(OD)/METAL1/CONTACT) - to be connected to VDD or power supply or you can surround an ntap ring to your PMOS type elements.
ptap contact -consist of the following layers (PPLUS/ACTIVE(OD)/METAL1/CONTACT) - to be connected to GND or ground or you can surround a ptap ring to your NMOS type elements.
ntap contact -consist of the following layers (NWELL/NPLUS/ACTIVE(OD)/METAL1/CONTACT) - to be connected to VDD or power supply or you can surround an ntap ring to your PMOS type elements.
ptap contact -consist of the following layers (PPLUS/ACTIVE(OD)/METAL1/CONTACT) - to be connected to GND or ground or you can surround a ptap ring to your NMOS type elements.
hi, after reading this ,i know how to do in CMOS, but if the SiGe BiCMOS technology is used, then , how to do with the npn transistor, where can i draw with the ntap contact and the ptap contact. would you plz give an example with a picture.