ibrary IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity computation2 is
port (
Clock: in STD_LOGIC;
reset: in STD_LOGIC;
Digit: in STD_LOGIC_VECTOR (23 downto 0);
DigitValid: in STD_LOGIC;
F1: out STD_LOGIC_VECTOR (27 downto 0);
deltaF: out STD_LOGIC_VECTOR(27 downto 0)
);
end computation2;
architecture computation2 of computation2 is
signal I_WordNumber:INTEGER;
signal I_FC:INTEGER;
signal I_BW:INTEGER;
signal I_BW1:INTEGER;
signal I_WRF:INTEGER;
signal I_F1:INTEGER;
signal I_DF:INTEGER;
begin
process (Clock,DigitValid,reset)
begin
if (reset='1') then
I_WordNumber <=1;
I_BW <=1;
I_WRF <= 1;
I_FC<=1;
I_DF<=0;
elsif (DigitValid'Event and DigitValid='0') then
if(I_WordNumber=1) then
I_BW <= CONV_INTEGER(Digit);
I_WordNumber<=2;
elsif(I_WordNumber=2) then
I_BW <= I_BW*1000;
I_FC <= CONV_INTEGER(Digit);
I_WordNumber<=3;
elsif (I_WordNumber=3) then
I_FC <= I_FC*1000;
I_WRF<=CONV_INTEGER(Digit);
I_WordNumber<=4;
elsif (I_WordNumber=4) then
I_WordNumber<=1;
I_F1 <= I_FC - (I_BW/2);
I_DF <= (I_BW * I_WRF * 114) / 300000000000;
end if;
F1 <= CONV_STD_LOGIC_VECTOR (I_F1, 28);
deltaF <= CONV_STD_LOGIC_VECTOR (I_DF, 28);
end if;
end process;
end computation2;