multiflop
When we talk about a bit synchronizer we never say its a 2-stage synchronizer; we say its a multi-flop synchronizer. It doesn't mean that it has only 2 registers in parallel.
This is an statement from the Atera's paper on metastability in FPGA's.
"To improve metastability MTBF, designers can increase tMET by adding extra register stages to synchronization register chains. The timing slack on each additional register-to-register connection is added to the tMET value. Designers commonly use two registers to synchronize a signal, but Altera recommends using a standard of three registers for better metastability protection. However, adding a register adds an additional latency stage to the synchronization logic, so designers must evaluate whether that is acceptable."
So in this case altera recommends "three" registers. So can we assume that there is a possibility that the second register in the synchronizer stage can also get into a metastable state.
So again my question is "How does one decide the number of synchronizer stages?". What kind of data helps one figure out the number of synchonizer stages required?