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Draw an inverter. Draw the layout. No, I use a P-well process (or whatever is opposite of what you draw) Redraw it.
Draw a 4-1 mux using transmission gates (or whatever they think you don't know based on how you answered #1)
What tools do you know? Do you know Verilog (or VHDL)? How many pins was the biggest project you have made? What was the die area? Power dissipation? How could you have made the power dissipation smaller? (answer - smaller/better process!)
Some places will give you a big schematic - why won't this circuit work? They want to see you work a problem - noone can solve it by looking at it!!! Trace it out, and explain why you make the choices you do. Be calm and simply work the way you do. Even if you turn out wrong, they will know you are well prepared to understand how to approach things.
Those are some of the questions I remember I liked, and turned out good for me. Or you could use Intel's "famous" question to some of their candidates (no not me - they work you too hard!!)..
You have one match, and 10 inches of candle wick that will burn in one hour. The candle wick does NOT burn at an even rate, meaning if you cut it in half, one half may burn in 50 minutes, the other in 10. You need to make a timer to count out 15 minutes, 30 minutes after it it lit. Good luck.
If you think, it is like a current source problem..
I know how to count out 30 minutes...
The way is : lights two ends of the wick at the same time,so when it burns out,the time just exactly past 30 minutes.
Can anyone tell me how to get 15 minutes? :wink:
can anyone tell me after u masters degree..what the major chip design companies expect from a student...do they ask for tool usage knowleedge or they go a lot into technical details...
there's a couple responses that i think were considered right. let me see if i remember them all
1) one was: fold in half, fold each end in half again.. now unfold the middle section and light the center. start counting when BOTH flames reach their own doubled-over (1/4) point, and stop when they are both out.
2) Next one was to fold the ends to the center, then fold one side to the center again. light the singly-folded end, and it should take 30m to get to the 4x folded area, and another 15m to burn out.
3) next one was something like cut in half, then cut in half again, then again to make 8 segments of 7.5 minutes each. You can now mix them enough to assume even burning with good mixing technique. the calculated error of this technique is 1/8th of the total burn time, which is half the time you need to measure.
-Not sure why that #3 is right. I think 1/2 error is too much. My answer was to cut into hundreds of tiny pieces, and make two piles of size x and size 2x, touching in only a small area. light the 2x pile and by the time 2x is done is 30m, by the time that the whole thing is burned is another 15m.
It's not such a hard question - I think the idea was to equate to process variation. Never use an absolute value of resistance, only use ratios, etc. Never use an absolute value of current, just use W/L ratios. Not like Intel is an analog company, but these are just general guidelines of design.
- to amarnath. I find the tools do not matter. Its best to know one flow, but tools are tools. Schematic capture and simulation are pretty much equivalent in any design platform. If you are a beginning designer you are not expected to know every toolset. You ARE expected to work very hard in order to learn your new company's tools, though so it does not delay your ability to produce.
How can you fold like that since it's possible that one pecent of this candle may take 59 min to burn out. At least we should know the variation range, then talk about a measurement with in required accuracy. Am I right?
I met a similar question before, but you have 2 candle, and 45 minutes. so the answer is :
1) light 2 ends of a candle, 1 end of a candle at the same time.
2) after 30 minutes, 1 candle burn out. now light the other end of the left candle, you get 15 minutes.
Hello,
I think that you have to start burning both ends at the same time. When 50 cm of unburned wick remains, you have your 15 min timer. When no burned wick remains you have your 30 min timer.
The solution is general and not depends on the linearity of the function of time elapsed vs length of burned wick. Just no first derivative sign change in this function ( more than reasonable, wick can not burn backwards )
hello amarnath,
most of the companies,(Bachelors/masters) ask only the basic question. for ex what is latch ? what is MSFF ? write timing daigrams ? etc.
if you are tro this round then they will ask some question on the analog part (very basic).
after this some questions of the VHDL/Verilog languages.
and some questions on your VLSI design flow.
and some questions on your projects(VLSI projects)
they don't expect high fundas only basic of the above mentioned topics.
. Explain how a MOSFET works, should explain in drawing of cross section of mosfet in cmos process
2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation
3. Explain the various MOSFET Capacitances & their significance
4. Draw a CMOS Inverter. Explain its transfer characteristics
5. Explain sizing of the inverter
6. How do you size NMOS and PMOS transistors to increase the threshold voltage?
7. What is Noise Margin? Explain the procedure to determine Noise Margin
8. Give the expression for CMOS switching power dissipation
9. What is Body Effect?
10. Describe the various effects of scaling
11. Give the expression for calculating Delay in CMOS circuit
12. What happens to delay if you increase load capacitance?
13. What happens to delay if we include a resistance at the output of a CMOS circuit?
14. What are the limitations in increasing the power supply to reduce delay?
15. How does Resistance of the metal lines vary with increasing thickness and increasing length?
16. You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
17. What happens if we increase the number of contacts or via from one metal layer to the next?
18. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
20. Draw the stick diagram of a NOR gate. Optimize it
21. For CMOS logic, give the various techniques you know to minimize power consumption
22. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
23. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
24. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
26. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
27. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
28. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
29. Draw a 6-T SRAM Cell and explain the Read and Write operations
30. Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
31. What happens if we use an Inverter instead of the Differential Sense Amplifier?
32. Draw the SRAM Write Circuitry
33. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance?
35. What’s the critical path in a SRAM?
36. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
37. Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
38. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
39. How can you model a SRAM at RTL Level?
40. What’s the difference between Testing & Verification?
41. For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
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