Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

NMOS pass characteristics

Not open for further replies.


Junior Member level 1
Apr 28, 2012
Reaction score
Trophy points
Activity points
hello... every one.
i'm newer in this field.

i have a small doubt about pass characteristic of nmos transistor.

if i will give Vdd=1.8 v (logic ' 1' ) to the gate terminal and its drain terminal has also 1.8 v then source will go up to maximum voltage level Vdd-Vtn.
now if i change the transistor width up to 30 times greater then its length then will my source exceed Vdd-Vtn level and reach nearer to Vdd ?

thanks in advance...

Think of it in this way.

If the gate is at Vgate and the drain is at Vdrain, The source terminal can go up to Vgate-Vth beyond which the transistor would turn off.

If the source is above the Vgate-Vth level, the transistor is OFF and the the switch is open.
This is why a NMOS is a better pass device for logic 0 and a PMOS is a better device for logic 1.

You can use a complementary pass switch using both NMOS and PMOS to solve this problem.

Well width and length does not matter in this case and you can never go beyond Vdd-Vtn. You need to understand the working of NMOS and various regions it can work in. For NMOS to pass current and act as switch, a minimum difference in voltage of Vtn should exist between gate and source, i.e. Vgs => Vtn.
When you try to increase source voltage > Vdd-Vtn, this condition is violated and NMOS enters into cut off state.

thank you for information.

Not open for further replies.

Part and Inventory Search

Welcome to