NMOS gate at a voltage lower than source and bulk voltages

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mvj

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Hi All,

May I know what would happen if the gate is connected to a voltage lower than that of the source and the bulk.

Say
Vs = 0V
Vbulk = 0V
Vd = 5V
and Vg = -1V

Theoretically, this means taht the device would not turn on but I would like to know there would be issues in an actual physical device. My understanding is that if |Vgb| is more than the max Vgb allowed, it would lead to punch through. What about the source and drain terminals, will they be effected in any way.

Thanks a lot in advance!!
M
 

Hi mvj

there are devices that can actually benefit from bringing the gate below source as it reduces drain-source leakage (e.g. 0-Vt devices);
I doubt that a device that can tolerate 5 volt on the drain will be bothered by -1V on the gate;
I don't think punch-through has much to do with gate voltage as it requires source and drain depletion regions to merge, which is mostly defined by Vdb and Vsb;
Vgb will become a problem when it reaches the same absolute value as the maximum gate voltage of the process (the electric field across the oxide will be the same)
If you keep lowering the gate voltage i would think that the first limit you'd encounter is Vdg, hot electrons a the drain are bound to make some damage at some point
 
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    mvj

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If you take the gate too far negative, and have a high drain
voltage the field sum will begin to increase drain current
above the zero-VGS leakage floor. Look up "GIDL". You can
see this in ID-VG curves of real transistors if you take it far
enough negative.
 
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    mvj

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    dgnani

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