I would try to emulate how semiconductor fab folks and
modeling folks test it - apply a voltage ramp, acquire the
current as you go, and do the math (integral of I being
Q, Q being C*V, at any given V your C is I/(dV/dt).
Pretty easy to set up if you have a Calculator in your
waveform viewer with a deriv() function. Or you could
dump raw data if it's ASCII SPICE (does anybody still
work that way?).
I=C*dV/dt would give you a nice simple result, in the I,
if you scaled your ramp dV/dt just-so. Like say 1V/1mS
then your C=I/1m. And your V is the (also scaled) time
axis.
NMOS vs PMOS - check polarity. You only see C-V swing
when you cross from accumulation to inversion. Outside
this you see roughly constant C. Not "nothing", just nothing
changes.
Poly caps (presuming you mean a "POP" cap - MOS caps
are poly-Tox-Si) give you a free hand with both terminals,
where MOS caps include a large parasitic diode*cap to
the substrate or well. OK for shunt (as long as nonlinearity
doesn't bother you) but needing to be applied right as a
series element and lossy at one end (at best - possibly
a bind for drive, with the diode action). Beware a "mos cap"
model, be sure it includes a realistic body diode and not
just some warning somewhere in the design manual that
you didn't read, about this).
POP caps need two layers of poly, which may be "ala carte"
(usually only found on mixed-signal targeted technologies,
it's irrelevant expense for a "digital" CMOS flow.
A MOS cap almost certainly has the advantage in regard to
capacitance per area (density).