NMOS AND2 and NAND2 Circuit? How?

[2wice]

Can someone explain to me or show me a circuit where AND and NAND can be made using only with nMOS rather than with pMOS and nMOS. I think if one of those is inverted then we could get the other and NMOS inverter is easy.

 

[FvM]

Message is unavailable.

 

[2wice]

Thanks a lot. Can you explain to me what the VGG is for? Is VGG = VDD?

 

[wizard of oz]

VGG sets the logc 1, i.e. 1=Vgg-Vth. Ideally should be larger that VDD, but VDD works too.

 

[FvM]

VGG sets the logc 1, i.e. 1=Vgg-Vth. Ideally should be larger that VDD, but VDD works too.

The paper discusses different types of transistor loads, using both enhancement (Vt>0) and depletion mode (Vt<0) transistors. In practice, it depends on available transistor technology. I think that the circuits at page 10 ("Static AND, OR & XOR Gates") are realistic examples.