13579
Newbie
Hello all,
I am wondering if someone could help me with designing a 5th Order Butterworth LPF using a Switching Capacitor topology in NI Multisim 13.0?
I am trying to replicate a design used in "Design with Operational Amplifiers and Analog Integrated Circuits" by Sergio Franco in Figure 4.33 using Ideal components, where the component values have been worked out in Example 4.13 for f_c = 1kHz at a f_ck = 100kHz and providing the following capacitor values:
C_Ri = C_Ro = C_0 = 1pF, C_C1 = C_C5 = 9.84pF, C_L2 = C_L4 = 25.75pF, and C_C3 = 31.83pF.
The circuit looks like so (note all components are Ideal):
View attachment SC 5th Order Butterworth  Circuit.pdf
With the heirachal inverting blocks implemented like so:
View attachment SC 5th Order Butterworth  Circuit  Inverting Switch Block.pdf
View attachment SC 5th Order Butterworth  Circuit  Inverting Switch Block 2.pdf
The resulting Bode Plot is nothing like a LPF:
View attachment SC 5th Order Butterworth  Bode.pdf
The Transient @ 100Hz looks somewhat reasonable, though it is clipping on the negative swing:
View attachment 5th Order Butterworth  Transient @ 100Hz.pdf
And the Transient @ 1kHz is starting to go wrong:
View attachment 5th Order Butterworth  Transient @ 1kHz  2.pdf
But then @ 10kHz, it completely disappears:
View attachment 5th Order Butterworth  Transient @ 10kHz.pdf
For reference, here are my clock pulses (clk_phi and clk_phi_bar):
View attachment SC 5th Order Butterworth  Clock.pdf
Can Switched Capacitor circuits be simulated in NI Multisim 13.0?
As it is, I had a convergence problem and needed to relax ABSTOL to 1e008A and VNTOL to 0.0001V in order to simulate the results. Someone had mentioned that because the convergence is being done at specific points in time, that a switched capacitor system might not be able to simulate correctly, and especially wouldn't bode plot correctly.
Eventually I want to implement this circuit topology with a 7th Order Butterworth and a clock that is upwards of 10MHz, but for the present, I would be satisfied with just getting this circuit to work as expected.
Multisim Circuit Files can be found in the zip file below:
View attachment SC 5th Order LPF.zip
Thanks for the time and assistance.
I am wondering if someone could help me with designing a 5th Order Butterworth LPF using a Switching Capacitor topology in NI Multisim 13.0?
I am trying to replicate a design used in "Design with Operational Amplifiers and Analog Integrated Circuits" by Sergio Franco in Figure 4.33 using Ideal components, where the component values have been worked out in Example 4.13 for f_c = 1kHz at a f_ck = 100kHz and providing the following capacitor values:
C_Ri = C_Ro = C_0 = 1pF, C_C1 = C_C5 = 9.84pF, C_L2 = C_L4 = 25.75pF, and C_C3 = 31.83pF.
The circuit looks like so (note all components are Ideal):
View attachment SC 5th Order Butterworth  Circuit.pdf
With the heirachal inverting blocks implemented like so:
View attachment SC 5th Order Butterworth  Circuit  Inverting Switch Block.pdf
View attachment SC 5th Order Butterworth  Circuit  Inverting Switch Block 2.pdf
The resulting Bode Plot is nothing like a LPF:
View attachment SC 5th Order Butterworth  Bode.pdf
The Transient @ 100Hz looks somewhat reasonable, though it is clipping on the negative swing:
View attachment 5th Order Butterworth  Transient @ 100Hz.pdf
And the Transient @ 1kHz is starting to go wrong:
View attachment 5th Order Butterworth  Transient @ 1kHz  2.pdf
But then @ 10kHz, it completely disappears:
View attachment 5th Order Butterworth  Transient @ 10kHz.pdf
For reference, here are my clock pulses (clk_phi and clk_phi_bar):
View attachment SC 5th Order Butterworth  Clock.pdf
Can Switched Capacitor circuits be simulated in NI Multisim 13.0?
As it is, I had a convergence problem and needed to relax ABSTOL to 1e008A and VNTOL to 0.0001V in order to simulate the results. Someone had mentioned that because the convergence is being done at specific points in time, that a switched capacitor system might not be able to simulate correctly, and especially wouldn't bode plot correctly.
Eventually I want to implement this circuit topology with a 7th Order Butterworth and a clock that is upwards of 10MHz, but for the present, I would be satisfied with just getting this circuit to work as expected.
Multisim Circuit Files can be found in the zip file below:
View attachment SC 5th Order LPF.zip
Thanks for the time and assistance.
Attachments

397.2 KB Views: 3
Last edited: