nexys 3 FPGA board with PmodBT2

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:29:26 04/13/2015
//////////////////////////////////////////////////////////////
module Uart_Rec(clk,Rx,PMODBT_RST,output2);
input clk;
input Rx;
output reg [7:0]output2;
output PMODBT_RST;
 
 
reg [9:0]Reg_a=10'b1111111111;
reg alpha=0;
reg [3:0]i=4'b0000;
reg e=0;
reg [9:0]counter=10'b1000001001;
 
assign PMODBT_RST=1;
 
 
always @(posedge clk) begin
output2 = (Reg_a[9] == 1 && Reg_a[0]==0 ) ? Reg_a[8:1] :output2;
if (e==1) begin
if (counter < 10'b1000001001) begin counter=counter+1'b1; end
else begin counter=0; end
alpha = (counter==0) ? (~alpha):alpha;
 
end
e= (Rx==0)? 1'b1:e;
e= (i> 5'b1001) ? 1'b0:e;
counter = (e==0) ? 8'b11111111:counter;
end
 
 
always @( posedge alpha) begin
if(e>0 && i<10) begin
Reg_a[i]=Rx;
i=i+1'b1; end
i= (i> 5'b1001) ? 4'b0000:i;
end
 
endmodule