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New technique for pulse-width functions

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sdc18

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Hey all,

I am beginning to write a paper on a new technique for making pulse-width generators on FPGAs and I was hoping I could get some help connecting it to the current state-of-the-art and get suggestions for some applications.

My circuits use a new technique for laying out logic elements. Each circuit maps an input pulse of width w_{in} to an output pulse of width w_{out} through any arbitrary function f(w_{in})=w_{out}. The function f can be linear, quadratic, etc. and the resolution of the function is the minimum gate delay ~300ps. Again, this is an asynchronous circuit, so there is little to no latency.

What similar technologies are out there?
What applications can this have? I have been using it for an arbitrary pulse-width doubling circuit, but I suspect there are better applications in other areas of engineering.

I am also looking for helpful references for my paper.

Thanks!
 

The problem with anything asynchronous on an FPGA is that the delay is affected by many things: Process, voltage, temperature and Place and Route.
You can lock down the P&R yourself, but you have no control over the other three.

How will your circuit overcome these delay/timing issues?
What about the routing delay?

PS. Gate Delay not really a term applicable to FPGAs. It has no internal gates - just LUTs that can map to many gates.
 

I agree that temp., voltage, etc. can affect the timing of performing logic operations through the LUTs. Right now, my technique is just a proof-of-concept. I have developed the theory for why it should work and used the FPGA as a platform to test it. Ultimately, an ASIC could be created (with much more control over these parameters) for each pulse-width function that is desired.

Also, as far at the place and route, I can control these, in addition to the paths through the individual LUTs. However, these factors only lead to small discontinuities in the function f(w_{in}) = w_{out}, and the global function retains its shape even if I let the optimizer do its thing.

I guess I am asking, what could this be used for? What is similar that is out there?

Right now, the only types of pulse-width control circuits that I know of seem to be limited by the clock or some other on-board oscillator.

Thanks!
 

Each circuit maps an input pulse of width w_{in} to an output pulse of width w_{out} through any arbitrary function f(w_{in})=w_{out}. The function f can be linear, quadratic, etc.

If both inputs and outputs signals are in the PWM format, you´re certainly aware that the range of these function should be limited to full scale of the pulse width, in supposing that the gain of the function is >1.

A circuit like that could be used to compensate the non linearity read from some measure but I particularly can't see any application on what a predetermined simple function would be used ( linear, quadratic, etc... ) having just one of these components. In general the electric phenomena happens behaving much more like a polynomial model, whose weight parameters differs in each case.
 
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    sdc18

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If both inputs and outputs signals are in the PWM format, you´re certainly aware that the range of these function should be limited to full scale of the pulse width, in supposing that the gain of the function is >1.

What do you mean by "PWM format"? For my circuit, I inject a single pulse in and get out a single pulse. There is no repetition.

Can you elaborate on what you mean by this? Why is the range limited to the scale of the pulse-width? I can make the pulse grow without a limiting range with a function w_{out} = f(w_{in}) = 2*w_{in}. For my technique, the limit on w_{out} is the number of logic elements I use.
 

Ok, I did not realize the working of this function; I presumed that would be applicable to digital systems such as modulation that commonly operate cyclically processing a stream of pulses.

Anyway, though obvious, I was just mentioning that the width of the pulse on output should be smaller than interval to the subsequent sample.
 
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    sdc18

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