Back in the late '80s / early '90s I knew a guy out of TRW
Redondo Beach who told me about InP digital chips they were
doing, with 200GHz main clock.
While detailed design databases are probably still locked up
IP-wise maybe your university could make a deal with the
original vendor, or its successors, for IP access. However
you should expect that the design schematics are paper
and some reel tape archives that you can't find a reader
for (NMOS uPs are so '70s).
What about the notion of taking one of the open source
uP/uC projects, pick one that looks good, simple and able
to be speed-tweaked the way you want, and attack the
low level logic gate designs first, then go bottom-up? It's
not like there's a big difference between a depletion-load
inverter and CMOS (more, perhaps, in DFF design where
a HBT doesn't make so good a pass-switch for a TINV-
style DFF, but I'm sure you can find examples that work).
I might recommend you also consider what kind of processor
would actually useful in a >100GHz-clocked system, a general
purpose small processor probably isn't it. But a custom DSP,
suited to radio front end functions, sure could be.