AlexWan said:hi, good_kiss
For my opinion, the netlist simulation is the Gate-level simulation. After synthesis, you can get the netlist and the SDF file(only have the cell delay). Annotate the SDF file into your netlist, then simulate it for your dynamic timing verification.
After you finished the functional verification and synthesis, you must do the STA and netlist simulation for confirming your design. So it is on the critical path of design flow.
gerade said:still some designer believe to do the netlist simulation in an early stage will find some design issues, which can not be found by STA tools
regards
zyphor said:from experience we focus on STA, and if we have time we will run all the cases using final netlist with delay back annoted.
gerade said:Alexwan and other guys,
how about conformal. powerful? how about its runtime.
gerade said:it is amazing.
it seems that formal verification is extremely important for UDSM design.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?