I'm not sure why it isn't inferring dmem here, although that is still fairly large.
This looks somewhat like a RAM, other than the "only write 1" aspect being a bit odd as the design can't ever be reset without reprogramming the FPGA.
If valid can be registered, that would be more ideal. First because it is uncommon to have unregistered outputs. It would also allow this to infer block ram, which would map to a BRAM18 in devices that Vivado targets.
The large lut count is based on generating such a large number of write enables as well as a very large output mux.
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I'm not sure why it isn't inferring dmem here, although that is still fairly large.
This looks somewhat like a RAM, other than the "only write 1" aspect being a bit odd as the design can't ever be reset without reprogramming the FPGA.
If valid can be registered, that would be more ideal. First because it is uncommon to have unregistered outputs. It would also allow this to infer block ram, which would map to a BRAM18 in devices that Vivado targets.
The large lut count is based on generating such a large number of write enables as well as a very large output mux.