the issue is the multiplication should start withrespect to one clock signal ( say clk1) and from then proceed according to an another clock (clk 2)!!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
entity zcd01 is
Port ( clk : in std_logic;
d : out integer;
d1 : out integer;
op1 : inout STD_LOGIC;
res : out integer);
end zcd01;
architecture Behavioral of zcd01 is
type sine is array (0 to 16) of integer;
type sine2 is array (0 to 16) of integer;
signal val0 : sine := (7,4,2,0,0,1,3,6,9,11,13,14,14,12,10,7,0);
signal val : sine2 := (0,0,1,3,6,9,11,13,14,14,12,10,7,0,7,4,2);
signal c:integer:=0;
signal ptr : integer;
begin
process (clk)
constant ref :integer :=7;
begin
if rising_edge(clk) then
d <= val0(c);
d1 <= val(c);
if val (c) = ref then op1 <= '1';
else if (ref - val(c))<0 and (ref - val (c-1)) > 0 then op1 <= '1';
else op1 <= '0';
end if;
end if;
c <= c+1;
end if;
end process;
process (op1,clk)
begin
if op1' event and op1 = '1' then
ptr <= 0;
end if;
if rising_edge(clk) then
if ptr >= 0 then res <= val0(c) * val (c);
end if;
ptr <= ptr +1;
end if;
end process;
end Behavioral;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 signal op1_r : std_logic; process(clk) begin if rising_edge(clk) then op1_r <= op1; if ptr >= 0 then res <= val0(c) * val (c); end if; ptr <= ptr +1; if op1 = '1' and op1_r = '0' then -- rising_edge detection of op1 - reset ptr. ptr <= 0; end if; end if; end process;
ya, I got ur point. thank you for the code. but then how do I keep the code running even after c reaches 18? I need a cyclic process
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use IEEE.NUMERIC_STD.ALL;
entity scheme_demod is
Port (-- TX_DATA : in signed (16 downto 0);
--RX_DATA : in signed (16 downto 0);
--clk : in STD_LOGIC;
demod_clk : in STD_LOGIC;
-- rx_data_compl : in STD_LOGIC;
--tx_data_compl : in STD_LOGIC; -- will be high if all data values are send
b_count : out STD_LOGIC; -- to uart for completion and start of byte ( b_count =1 complete, b_count= 0 start)
start_data : out STD_LOGIC; --- to spiTX and spiRX ( if 0 means start sensding the data from tX)
start_data1 : out STD_LOGIC;
DATA_OUT : out std_logic_vector (39 downto 0);
op : inout std_logic :='0';
sin : inout signed(16 downto 0);
sin1 : inout signed(16 downto 0);
sin2 : inout signed(16 downto 0));
--temp_sum :inout integer);
end scheme_demod;
architecture Behavioral of scheme_demod is
type bus_type is array(0 to 23) of integer range 0 to 65535;
signal TX_DATA : bus_type :=(32767,40609,47995,54496,59735,63406,65296,63406,59735,54496,47995,40609,32767,24924,17538,11037,5798,2129,238,2129,5798,11037,17538,24924);
signal RX_DATA : bus_type :=(54496,59735,63406,65296,63406,59735,54496,47995,40609,32767,24924,17538,11037,5798,2129,238,2129,5798,11037,17538,24924,32767,40609,47995);
signal temp_sum : signed(39 downto 0) :="0000000000000000000000000000000000000000";
signal test : std_logic := '1';
signal test1 : std_logic := '1';
signal ptr: integer;
--signal sum :signed (39 downto 0):="0000000000000000000000000000000000000000";
type bus_type1 is array (0 to 23) of signed (16 downto 0);
signal temp_tx : bus_type1 :=(others =>(others => '0'));
signal temp_rx : bus_type1 :=(others =>(others => '0'));
signal temp : signed(39 downto 0) :="0000000000000000000000000000000000000000";
type bus_type2 is array (0 to 23) of signed (16 downto 0);
signal new_rx : bus_type2 :=(others =>(others => '0'));
--signal int : integer;
begin
start_data <= test ; --or test1; --- changed on 30/03/2016 from "test" to " or test1"
start_data1 <= test1;
process (demod_clk)
variable i : integer :=0;
variable a: integer :=0;
variable b : integer;
begin
if rising_edge(demod_clk)then
b_count <= '0';
temp_tx(i) <=to_signed( TX_DATA(i) - 32767,17);
temp_rx(i) <=to_signed( RX_DATA(i) - 32767,17);
if (0 - temp_rx(i)) > 0 and (0 - temp_rx(i+1)) = 0 then
op <= '1';
ptr <= i;
else
op <= '0';
end if;
i := i + 1;
end if;
if (i = 24) then
test <= '0';
i := 0;
end if;
--end if;
end process;
process(op,demod_clk)
variable j1: integer;
variable k,p : integer :=0;
variable p1 : std_logic := '0';
begin
if op' event and op = '1' then
p1 := '1';
j1 :=ptr+1;
end if;
if rising_edge(demod_clk) then
if p1 = '1' then
new_rx(p) <= temp_rx(j1);
sin <= temp_tx(p);
sin1 <= new_rx(p);
sin2 <= temp_rx(p);
temp_sum <= temp_sum + (temp_tx(k) * new_rx(k));
j1 := j1+1;
p := p+1;
k := k+1;
if (j1 = 24)then j1 :=0;end if;
end if;
end if;
if (k = 24) then
temp <= temp_sum + (temp_tx(k-1) * new_rx(k-1)) ;
DATA_OUT <= std_logic_vector(temp);
temp_sum <= "0000000000000000000000000000000000000000";
k := 0;
p := 0;
b_count <= '1';
test <= '1'; ---added on 30/03/2016 from "test" to " or test1"
end if;
end process;
end Behavioral;
so you think changing the variable will do the trick? i actually tried it once. i will try again
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