In general, the setup/hold time is positive. But, to help the design, we often design negative hold time for flip/flop, memory and so on, then designer only has to fix setup time violation.
In your SDF, there ofter are negatve timing.
Let me has an example, when the input signal of one buffer has big transition, the output signal of the buffer will has much small transition. As DC is using 1/2 vdd as switching point, but actually not, it somehow likes that the output signal is before input signal, then negative timing appears.