Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Negative HOLD or SETUP timingcheck in SDF file

Status
Not open for further replies.

sisari

Junior Member level 3
Joined
Sep 3, 2001
Messages
26
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
122
I am newbie in ASIC design and want to ask what does a negative setup
or hold timecheck in an DC generated SDF file means. I need some help
in understanding the SDF for sequencial components.
 

mami_hacky

Full Member level 6
Joined
Mar 28, 2002
Messages
337
Helped
18
Reputation
36
Reaction score
11
Trophy points
1,298
Location
Some where
Activity points
3,428
I do not know any thing about a negative setup time, But negative hold time can be completely natural. Suppose that you are designing a circuit using SSTL2 I/O signaling standard. Simply you will find that the hold time for I/O circuits is negative. What is the reason? And what does it mean? a negative hold time, means that you can change the data on the input pad of your ASIC/FPGA before I/O register's (neg or pos) clock edge. I think a simple picture will describe this well.
Negative hold time is the result of I/O circuit design, have a look at DDR SDRAM datasheets to find out more about it.

Any thing wrong in the above text?
 

albertyin

Junior Member level 1
Joined
May 12, 2004
Messages
16
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
103
In general, the setup/hold time is positive. But, to help the design, we often design negative hold time for flip/flop, memory and so on, then designer only has to fix setup time violation.
In your SDF, there ofter are negatve timing.
Let me has an example, when the input signal of one buffer has big transition, the output signal of the buffer will has much small transition. As DC is using 1/2 vdd as switching point, but actually not, it somehow likes that the output signal is before input signal, then negative timing appears.
 

AlexWan

Full Member level 5
Joined
Dec 26, 2003
Messages
304
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Activity points
2,692
albertyin said:
Let me has an example, when the input signal of one buffer has big transition, the output signal of the buffer will has much small transition. As DC is using 1/2 vdd as switching point, but actually not, it somehow likes that the output signal is before input signal, then negative timing appears.
Thank you for your explain.
How to reduce , even prevent the negative timing appearing? modify the constraints or other ways ?
 

gerade

Advanced Member level 4
Joined
May 4, 2004
Messages
109
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Location
the hole eletron left behind
Activity points
1,014
negative hold time,
it is simply that the transition time of the siganl going to be capture is so short, it changes just before you store it in the register.

read book from Rabaey
 

Monkey

Newbie level 6
Joined
Apr 26, 2004
Messages
13
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
118
Negative Setup time can be solved by slowing down your clock or applying tightter cycle constraints during synthesis.
Negtive hold time can be sovled by properly arrange your clock. For example, design an low skew clock or route clock traces opposite the signal propagation direction.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top