negative edge detector

[ASIC_intl]

can u give an negative edge detector circuit?

 

[dcreddy1980]

always@(posedge clk or posedge reset)
begin
if(reset) begin
q_tmp <= 1'b0;
q <= 1'b0;
end
else begin
q <= d;
q_tmp <= q;
end
end

assign neg_edge = ~q & q_tmp;

where d is u r input pulse.

Bad at drawing the schematic and thats why i have written a verilog code.