Sep 9, 2008 #1 A ASIC_intl Banned Joined Jan 18, 2008 Messages 260 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,298 Activity points 0 can u give an negative edge detector circuit?
Sep 9, 2008 #2 D dcreddy1980 Full Member level 5 Joined Dec 3, 2004 Messages 241 Helped 46 Reputation 92 Reaction score 21 Trophy points 1,298 Location Munich, Germany Activity points 1,532 always@(posedge clk or posedge reset) begin if(reset) begin q_tmp <= 1'b0; q <= 1'b0; end else begin q <= d; q_tmp <= q; end end assign neg_edge = ~q & q_tmp; where d is u r input pulse. Bad at drawing the schematic and thats why i have written a verilog code.
always@(posedge clk or posedge reset) begin if(reset) begin q_tmp <= 1'b0; q <= 1'b0; end else begin q <= d; q_tmp <= q; end end assign neg_edge = ~q & q_tmp; where d is u r input pulse. Bad at drawing the schematic and thats why i have written a verilog code.