Negative edge D flip flop with synchronous active low set

[Abdul mohsin]

can any one draw the circuit of Negative edge dff with synchronous active low set ..actually i draw the circuit but am getting the wrong outputs by using the tool..so can any one suggest r any link for this cell....

 

[barry]

Is this an ASIC design question? If so, you've posted in the wrong forum.

 

[prestonee]

it might help to know what you are asking for is called a negative edge, or falling edge DFFR, active low set is called just a reset, DFFS and a DFFR and a DFFRS, set, reset, set or reset depending on which node is tied low. I havent come across many synchronous sets or resets, but you could easily turn any dffr into having a synchronous reset by adding a latch on the reset node. I believe I have used something like this a few years back but it was a handmade synchronous reset dffr using pass fets. I also agree with barry this should be in asic.

 

[mrflibble]

Mmmh? Not to be pedantic, but a DFFR clocked on negedge can occur in fpga designs as well, no? Or maybe I am missing something... But given that one generally uses posedge clocked FFs in fpga designs chances are that the OP is indeed doing something asic-ey.

 

[Abdul mohsin]

I can't get it

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sory i 4rget this is Asic