need your help ! for study Xilinx application( xapp264)

[Matrix_YL]

Hi all


I am studying xilinx's system generator ,using xapp264 for practice.
(The datasheet said "To conserve hardware, the filter is configured to oversample at a rate of four. The oversampled filter runs at the system rate (i.e., the same rate as the OPB clock), and therefore the filter data rate is four-cycles per sample." page 4 ,last segment)

but I don't understand why "coef_data" signal needed to be downsample at a rate of four when it output from FIFO. who can make it more clearer?

whether it means the FIFO of depth 32 in mem_if_in subsystem(Figure 12,page11) will be writen to full four times for write all coef_data to 32 tap fir just because of downsample as a rate of four ?
( I means due to FIFO of 32 depth when 32 words coef _data pass into downsample block at a rate of 4 , just 8 words coef_data will be sampled and out to 32 tap fir one times ,so for 32 coefficients need four times )


thank you

 

[echo47]

Please conserve EDAboard bandwidth. The app note is here:
https://www.xilinx.com/bvdocs/appnotes/xapp264.pdf

 

[Matrix_YL]

Hi all

I use OPB Export Tool export XAPP264 Reference Design(opb_sgp_filter.mdl) to EDK(system.xmp) as peripheral according to datasheet indicate but fail to implement (my tools are ISE 7.1.04i EDK SP2 ,System generator 7.1)

EDK Export.log show this

EDK Export log: Wed, 11-Jan-2006, 21:15:10
Done processing arguments
opb_sgp_filter 
D:/MATLAB7/toolbox/xilinx/sysgen/plugins/compilation/OPB Export Tool 
1 
 
system can not find directory 
EDKWrapperBuilder failed
error: EDKWrapperBuilder failed

what 's wrong with it ?

thanks in advance