jcpu
Full Member level 4
Dear Sir,
Working upon EPC GEN2 tag design, digital state machine part.
Need verilog (VHDL) test bench (or call it reader emulator program)
to test functionality of our verilog program.
Thanks in advance,
Working upon EPC GEN2 tag design, digital state machine part.
Need verilog (VHDL) test bench (or call it reader emulator program)
to test functionality of our verilog program.
Thanks in advance,