Need to slit a logic_vector - opposite of concatenate

[GreenP]

Concatenate

Hi

Could someone please help me as I require to slit a logic_vector, the opposite of the concatenate operator which i understand. For example if i have an eight bit vector how can i split the upper nibble from the lower nibble to form two four bit vectors?

Thanking you

GreenP

 

[trekkytekky]

Concatenate

Is this in VHDL?

 

[nareshgtr]

Re: Concatenate

In VHDL.. I hope following code will give answer for your questions

signal x: std_logic_vetctor(7 downto 0);
signal y: std_logic_vector (3 downto 0);
signal z: std_logic_vector (3 downto 0);
begin
y <= x(7 downto 4);
z <= x(4 downto 3);

 

[GreenP]

Re: Concatenate

Cheers thanks for your help