Need test suit for verification of Floating Point arithmetic unit

Similar threads

• S

  Floating point IP cores Latency problem

  • Started by Soh_bhat
  • Mar 28, 2023
  • Replies: 5

  PLD, SPLD, GAL, CPLD, FPGA Design
• C

  Seeking Help with VHDL Timing Issue in Arithmetic Operation

  • Started by chandra1502
  • Aug 29, 2023
  • Replies: 8

  PLD, SPLD, GAL, CPLD, FPGA Design
• S

  My VHDL Code is giving unexpected value after simulating with Floating point IP cores

  • Started by Soh_bhat
  • Apr 1, 2023
  • Replies: 5

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  [SOLVED] VHDL Based N-point FFT with fixed point package really slow, suggestions or improvements?

  • Started by mhmert
  • Aug 17, 2023
  • Replies: 13

  PLD, SPLD, GAL, CPLD, FPGA Design
• J

  [SOLVED] Distributed arithmetic: 2BAAT hardware with a single LUT

  • Started by Joshyan
  • Nov 28, 2022
  • Replies: 0

  PLD, SPLD, GAL, CPLD, FPGA Design