Need suggestions to remove Verilog warnings

[dpaul]

Hi all,

For my complete rtl, Cadence IRUN shows no problems and no warnings.

By when I am doing a LEC using Cadence Conformal(rtl VS netlist), then I get two warnings on my rtl which I have no idea how to get rid of.

--------------------------------------------
Code where warning is shown.....
I get warning msg on the FUNCTION

module my_module
#(
parameter AHB_AREA_START = 32'h0000_0000,
parameter AHB_AREA_SIZE = 32'h0004_0000,
parameter REG_ADDR = 32'h0004_3000
)
.
.
.
.

localparam VALID_ADDR_BITS = log2(AHB_AREA_START + AHB_AREA_SIZE - 1);

function integer log2;
input [31:0] value;
for (log2=0; value>0; log2=log2+1) /* Warning line 1 */
value = value>>1; /* Warning line 2 */
endfunction
.
.
.

-------------------------------------------------------------------

Warnings......

1> On Warning line 1 -
"Comparison with signed & unsigned operands"
("value>0" part of the for loop is highlited)

2> Warning line 2 -
"Input signal is assigned by logic values"
("value" text is highlited)

----------------------------------------------------------------------

Any type of guidance would be of great help!

Thanks in advance,
DP

 

[nkznzf]

Hi all,
function integer log2;
input [31:0] value;
for (log2=0; value>0; log2=log2+1) /* Warning line 1 */
value = value>>1; /* Warning line 2 */
endfunction
.
.
.

-------------------------------------------------------------------

Warnings......

1> On Warning line 1 -
"Comparison with signed & unsigned operands"
("value>0" part of the for loop is highlited)

2> Warning line 2 -
"Input signal is assigned by logic values"
("value" text is highlited)

----------------------------------------------------------------------

Any type of guidance would be of great help!

Thanks in advance,
DP

1, I really don't know what you compare, you mean that you compare value with zero, i think you should use value != 0
2, you assign to input??? it's wrong, man.