Hi, I want to design a circuit that :
input is pulse with different width, but i just want to have first pulse in output. do you have any idea to design this with gate level.
I will appreciate if someone help.
thanks
Hi, I want to design a circuit that :
input is pulse with different width, but i just want to have first pulse in output. do you have any idea to design this with gate level.
I will appreciate if someone help.
thanks
Your description is not very good, it takes time to find out what you mean.
No voltage, no frequency, no timing, ni diagram....
So maybe a flipflop that is set with the falling edge of the pulse.
Inver this output and feed it to an AND gate.
Second input of the AND gate is your input pulse.
Output of the AND gate is the output pulse.
You don't say if it is ever being activated again...
I write this idea for my purpose with verilog code
Code:
module pulseD(
input data_in, rst,
output reg data_out);
reg [3:0] count;
reg temp_in;
always @(*)
begin
temp_in <= data_in;
if (rst) begin
count <= 0;
end
else if (temp_in != data_in) begin
count <= count + 1;
end
end
always @(*)
begin
if (count <= 2'b10) begin
data_out <= data_in;
end
else
data_out <= 0;
end
But I want to design it with gates, Sorry for my poor writing, I wish you understand
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something like that. this picture is my output simulation of verilog code
So, if this cant work. what is your advice for me, I want to design a simple gate level circuit that work like this simulation :
It means in output I need just first pulse of my signal.
So, if this cant work. what is your advice for me, I want to design a simple gate level circuit that work like this simulation :View attachment 141260
It means in output I need just first pulse of my signal.
nothing makes sense here. you DO NOT want to design gate level, you want to design at RTL level and synthesize to gates. just google a template for synchronous counter in verilog and take it from there.
just for determine number of level changer, So I can use it, whenevre 2 times input level changed, output = input after that output = 0.
So with this idea output show just first pulse of input.