Need some help on desing of ADC

Thread starter deepu_s_s
Start date Dec 27, 2008

Status: Not open for further replies.

Dec 27, 2008

deepu_s_s

Full Member level 5

Hi all,

I am designing ADC in verilog. The first block i need to design is a sampler. The specifications are as follows

Signal frequency : 1KHz
Sampling Frequency : 2Khz
over samppling : 10 % of sampling

So the new sampling frequency is 2.2 KHZ...

Can anyone give some idea how to implement. No code is required.

Replies required asap

Thanks and Regards
Deepak

Status: Not open for further replies.

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Need some help on desing of ADC

deepu_s_s

Full Member level 5

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