lois1104
Newbie level 1
Hi, everyone!
I'm a beginner at VHDL coding. Recently in a project, we need to transfer data between two clock domains. These two clocks probably at the same frequency but with asynchronous phase. So I use async FIFO. The attachments include the VHDL codes and the testbench (not perfect). I don't know if it is fully correct.
I will be so appreciate if someone can give me some comments.
I'm a beginner at VHDL coding. Recently in a project, we need to transfer data between two clock domains. These two clocks probably at the same frequency but with asynchronous phase. So I use async FIFO. The attachments include the VHDL codes and the testbench (not perfect). I don't know if it is fully correct.
I will be so appreciate if someone can give me some comments.