library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD is
port(
LCD_RS:out std_logic;
LCD_RW:out std_logic;
LCD_E:out std_logic;
clk:in std_logic;
SF_D:out std_logic_vector(3 downto 0)
);
end LCD;
architecture Behavioral of LCD is
signal substate,clock,clk1: integer:=0;
signal state: integer:=0;
begin
process(clk)
begin
clk1<=clk1+1;
if(clk1=0) then
clock<=clock+1;
--WAIT FOR 750000 CLOCK
if(state=0 and clock=750000) then
state<=1;
clock<=0;
--WRITE SF_D=0X3 FOR INIATION
elsif(state=1) then
if(substate=0 and clock=0) then
LCD_RS<='1';
LCD_RW<='0';
SF_D<="0000";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0011";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=2;
Clock<=0;
end if;
--WAIT FOR 2050000 CLOCK
elsif(state=2 and clock=205000) then
state<=3;
clock<=0;
--WRITE SF_D=0X3 FOR INIATION
elsif(state=3) then
if(substate=0 and clock=0) then
LCD_RS<='1';
LCD_RW<='0';
SF_D<="0000";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0011";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=4;
Clock<=0;
end if;
--WAIT 5000 CLOCK
elsif(state=4 and clock=5000) then
state<=5;
clock<=0;
--WRITE 0X3 FOR INITIATION
elsif(state=5) then
if(substate=0 and clock=0) then
LCD_RS<='1';
LCD_RW<='0';
SF_D<="0000";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0011";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=6;
Clock<=0;
end if;
--WAIT 2000 CLOCK
elsif(state=6 and clock=2000) then
state<=7;
clock<=0;
--WRITE SF_D=0X2 FOR INITIATION
elsif(state=7) then
if(substate=0 and clock=0) then
LCD_RS<='1';
LCD_RW<='0';
SF_D<="0000";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0010";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=8;
Clock<=0;
end if;
--WAIT 2000 CLOCK
elsif(state=8 and clock=2000) then
state<=9;
clock<=0;
--WRITE FUNCTION SET SD_F = 0X28
elsif(state=9) then
if(substate=0 and clock=0) then
LCD_RS<='1';
LCD_RW<='0';
SF_D<="0010";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="1000";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=10;
Clock<=0;
end if;
--WAIT 2000 CLOCK
elsif(state=10 and clock=2000) then
state<=11;
clock<=0;
--WRITE ENTRY SET SF_D = 0X06
elsif(state=11) then
if(substate=0 and clock=0) then
LCD_RS<='0';
LCD_RW<='0';
SF_D<="0000";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0110";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=12;
Clock<=0;
end if;
--WAIT 2000 CLOCK
elsif(state=12 and clock=2000) then
state<=13;
clock<=0;
--WRITE DISPLAY ON /OFF SD_F=0X0C
elsif(state=13) then
if(substate=0 and clock=0) then
LCD_RS<='0';
LCD_RW<='0';
SF_D<="0000";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="1011";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=14;
Clock<=0;
end if;
--WAIT 2000 CLOCK
elsif(state=14 and clock=2000) then
state<=15;
clock<=0;
--WRITE CLEAR DISPLAY COMMAND SF_D<=0x HAVE TO FIX THIS
elsif(state=15) then
if(substate=0 and clock=0) then
LCD_RS<='0';
LCD_RW<='0';
SF_D<="0000";-- I HAVE FIXED IT
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0001";-- I HAVE FIXED IT
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=16;
Clock<=0;
end if;
--WAIT FOR 82,000 CLOCK
elsif(state=16 and clock=82000) then
state<=17;
clock<=0;
--WRITE SET DD RAM ADD SF_D<=0x HAVE TO FIX THIS
elsif(state=17) then
if(substate=0 and clock=0) then
LCD_RS<='0';
LCD_RW<='0';
SF_D<="1000";--IT HAS BEEN FIXED
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0000";-- IT HAS BEEN FIXED
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=18;
Clock<=0;
end if;
--WAIT FOR 2,000 CLOCK
elsif(state=18 and clock=2000) then
state<=19;
clock<=0;
--WRITE DD RAM ADD SF_D<=0x HAVE TO FIX THIS
elsif(state=19) then
if(substate=0 and clock=0) then
LCD_RS<='1';
LCD_RW<='0';
SF_D<="0100";--IT HAS BEEN FIXED
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0001";-- IT HAS BEEN FIXED
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=20;
Clock<=0;
end if;
elsif(state=20)then
state<=20;
clock<=0;
end if;
elsif(clk1=1) then
clk1<=0;
end if;
end process;
end Behavioral;
module top (clk, sf_ce0, lcd_rs, lcd_rw, lcd_e, lcd_4, lcd_5, lcd_6, lcd_7);
parameter k = 18;
(* LOC="C9" *) input clk; // synthesis attribute PERIOD clk "50 MHz"
reg [k+8-1:0] count=0;
(* LOC="D16" *) output reg sf_ce0; // high for full LCD access
reg lcd_busy=1;
reg lcd_stb;
reg [5:0] lcd_code;
reg [6:0] lcd_stuff;
(* LOC="L18" *) output reg lcd_rs;
(* LOC="L17" *) output reg lcd_rw;
(* LOC="M15" *) output reg lcd_7;
(* LOC="P17" *) output reg lcd_6;
(* LOC="R16" *) output reg lcd_5;
(* LOC="R15" *) output reg lcd_4;
(* LOC="M18" *) output reg lcd_e;
always @ (posedge clk) begin
count <= count + 1;
sf_ce0 <= 1;
case (count[k+7:k+2])
0: lcd_code <= 6'h03; // power-on initialization
1: lcd_code <= 6'h03;
2: lcd_code <= 6'h03;
3: lcd_code <= 6'h02;
4: lcd_code <= 6'h02; // function set
5: lcd_code <= 6'h08;
6: lcd_code <= 6'h00; // entry mode set
7: lcd_code <= 6'h06;
8: lcd_code <= 6'h00; // display on/off control
9: lcd_code <= 6'h0C;
10: lcd_code <= 6'h00; // display clear
11: lcd_code <= 6'h01;
12: lcd_code <= 6'h24; // H
13: lcd_code <= 6'h28;
14: lcd_code <= 6'h26; // e
15: lcd_code <= 6'h25;
16: lcd_code <= 6'h26; // l
17: lcd_code <= 6'h2C;
18: lcd_code <= 6'h26; // l
19: lcd_code <= 6'h2C;
20: lcd_code <= 6'h26; // o
21: lcd_code <= 6'h2F;
22: lcd_code <= 6'h22; //
23: lcd_code <= 6'h20;
24: lcd_code <= 6'h25; // W
25: lcd_code <= 6'h27;
26: lcd_code <= 6'h26; // o
27: lcd_code <= 6'h2F;
28: lcd_code <= 6'h27; // r
29: lcd_code <= 6'h22;
30: lcd_code <= 6'h26; // l
31: lcd_code <= 6'h2C;
32: lcd_code <= 6'h26; // d
33: lcd_code <= 6'h24;
34: lcd_code <= 6'h22; // !
35: lcd_code <= 6'h21;
default: lcd_code <= 6'h10;
endcase
//if (lcd_rw) // comment-out for repeating display
// lcd_busy <= 0; // comment-out for repeating display
lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy; // clkrate / 2^(k+2)
lcd_stuff <= {lcd_stb,lcd_code};
{lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
end
endmodule
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?