Need information regarding Transient Analysis output

[jdp721]

Hi.

I have a particular circuit block (to be precise, a switched capacitor 2nd order integrator), say block-A, which when transient simulated in Virtuoso ADE gives stable desired outputs.

Now, in the same schematic, when I am placing another circuit block-B (a regenerative comparator), without even any connection between the two blocks A and B, the transient output of block-A is showing ringing/oscillations !


It seems so strange that without any interaction between A and B, the output of A is getting affected due to the mere presence of B in the sch! Can anyone please explain this phenomenon?

Is it something like the presence of B is causing the simulator to decipher the ringing in A, which went otherwise unseen?!?

 

[Dominik Przyborowski]

Influence of supplies?

 

[jdp721]

Influence of supplies?

Sources that are common between the two blocks (when no other connection is there between blocks A and B) are a "vdc" and a "vpulse" source, and the "gnd" (all from analogLib of Cadence).
I do not think that this will lead to any interation....:|