I need some help to understand more about latch up failure.
Usually, latch up failure happens are due to improper layout of design OR due to process issue?
I heard that often latch up failure happens in IO mos. What are they for? Why it is often the case latch up happens at IO mos? Is the W/L bigger than normal logic mos or some other reason?
If anyone has any good reference on this topic, kindly share with me.
I think purpose of IO mos is to do ESD protection. It uses its parasitic diode to drain away ESD current. This parasitic diode is also forming the latch up transistors and if it doesn't take good care, it will induce latch up.
ESD protection and latch up is a trade off if you are using MOS. The better ESD protection the MOS can give, the easier latch up will happen to the MOS.
Thanks a lot everyone. Your advice are very useful. I am quite agree with what Seng Yee mentioned here and that leads me to some books to understand better. I indeed find some relation between ESD and IO device. Currently still reading for better digestion.....