[SOLVED] Need help with VHDL Reading from file

[LIFT]

Hi Guys,So sorry my first post here would be requesting for help.I am currently doing a project which is writing a Data Encryption Standard(DES)using VHDL,I am currently halfway done but I am having trouble reading from a input file.I entered 3 inputs and it could be written to a file.But when I put the 3 inputs in a file and tried to read from it,It doesnt work.

Please pardon my english,Below is my code(testbench) and input/output file,any help would be greatly appreciated,thanks for your time!

Input File(.txt)
___________________
785AC3A4BD0FE12D
123456789ABCDEF0
785AC3A4BD0FE12D


Output File(.txt)
___________________
1335 ns FD9CBA5D26331F38
2135 ns 17EA4A8B48C14DA0
2935 ns FD9CBA5D26331F38




Code
______________________________________________
library IEEE;
Use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
entity des_cipher_top_tb is end;
architecture key of des_cipher_top_tb is

component des_cipher_top port(

key: in std_logic_vector(0 to 63);

--
-- function select
--
function_select: in std_logic; -- active when encryption, inactive when decryption

--
-- input into des_cipher_top
--
data_in: in std_logic_vector(0 to 63);

--
-- input into des_cipher_top
--
data_out: out std_logic_vector(0 to 63);

--
-- data interface to MCU
--

--
-- General clock and reset
--
start_keyschedule: in std_logic;
start: in std_logic;
reset: in std_logic;
clock: in std_logic
);
end component;




signal reset, start,start_keyschedule: std_logic;
signal clock: std_logic := '0';

signal key:std_logic_vector(0 to 63);
signal function_select: std_logic;
signal data_in: std_logic_vector(0 to 63);
signal data_out: std_logic_vector(0 to 63);

signal key_in_internal: std_logic_vector(0 to 63);
signal memkey: std_logic_vector(0 to 63);

signal data_in_internal: std_logic_vector(0 to 63);
signal data_out_internal: std_logic_vector(0 to 63);


begin




u1:des_cipher_top port map(reset=>reset, clock=>clock, function_select=>function_select,
key=>key,data_in=>data_in,data_out=>data_out,
start=>start,start_keyschedule =>start_keyschedule);
start<= '0' ,
'1' after 600 ns,
'0' after 610 ns,
'1' after 1400 ns,
'0' after 1410 ns,
'1' after 2200 ns,
'0' after 2210 ns;
--'1' after 3000 ns,
--'0' after 3010 ns,
--'1' after 4560 ns,
--'0' after 4570 ns,
--'1' after 5100 ns,
--'0' after 5110 ns,
--'1' after 5800 ns,
--'0' after 5810 ns;
start_keyschedule <= '0',
'1' after 75 ns,
'0' after 85 ns;


reset<= '1', '0' after 50 ns;
--'1' after 4500 ns,
-- '0' after 4550 ns;
clock<= not clock after 5 ns;


-- data_in <= x"785AC3A4BD0FE12D",
-- x"123456789ABCDEF0" after 1400 ns,
-- x"785AC3A4BD0FE12D" after 2200 ns;

process
use std.textio.all;
use ieee.numeric_std.all;
file inputfile:text open read_mode is "input.txt";

variable ipa:std_logic_vector(63 downto 0);
variable inline:line;

begin
while not(endfile(inputfile))loop
readline(inputfile,inline);
read(inline,ipa);
data_in<=ipa;
wait for 4000 ns;

end loop;
wait;
end process;

function_select <= '1';
--'0' after 2100 ns,
--'1' after 4550 ns,
--'0' after 5800 ns;


tb: PROCESS
BEGIN
key <= x"38A84FF898B90B8F";
wait for 1400 ns;


end process;

process
use std.textio.all;
use ieee.numeric_std.all;
file resultfile:text open write_mode is "result.txt";
variable outline:line;

begin
wait on data_out;
wait for 50 ns;
write(outline,now,right, 2);
hwrite(outline,data_out,right, 40);
writeline(resultfile,outline);
end process;
end key;

 

[TrickyDicky]

So what exactly is the problem?

 

[LIFT]

Hi TrickyDicky,Thanks for the reply,the problem has actually been solved.I was being silly by forgetting to include a "h" in the reading part as my input is in hexadecimal.Hence,the code couldnt read from my input file.

Thanks for taking the time to read my thread!