Correct, I add that this aspect of VHDL is called OVERLOAD. This is a mechanism which permit to define more functions with the same name, the use of each function is based on the operand check (or "context" as alexan_e as mentioned). Then in VHDL exist more of one function called "<=". For example when "<=" work with two signals operands in a logic expression, it can make a comparison between their values, when it work with a signals but in a cuncurrent statement it perform an assigment action, the IDE resolve the functions in synthesis phase and will associate the right function to the operands.