Need help with VHDL Operators

[wo_osama]

I need to know what the difference between "=" and "<="
for example

architecture UPCOUNTER IS
begin
process(clk,rst)
begin
if rst='1' then cout <="000";
elseif rising_edge(clk) then cout <= cout +1;
end if;
end process;
end upcounter;


I need to know why is it we used "=" with if but "<=" with the rest, I usually pull it off by luck I don't give it a lot of thoght, but I have a lab exam tomorrow and I expect to be asked about these little things, so help needed, really appreciate it.
Thanks in advance.

 

[alexan_e]

if rst='1' then cout <="000";

This means if rst equals 1 then assign 000 to signal cout.

<= is the assignment operator for signals

Note that based on the context <= can also mean "less than or equal".

 

[shaiko]

as alexan_e said,
you should look at <= as a signle symbol - instead of looking at it as < and = seperated

 

[nanostallmann]

This means if rst equals 1 then assign 000 to signal cout.

<= is the assignment operator for signals

Note that based on the context <= can also mean "less than or equal".

Correct, I add that this aspect of VHDL is called OVERLOAD. This is a mechanism which permit to define more functions with the same name, the use of each function is based on the operand check (or "context" as alexan_e as mentioned). Then in VHDL exist more of one function called "<=". For example when "<=" work with two signals operands in a logic expression, it can make a comparison between their values, when it work with a signals but in a cuncurrent statement it perform an assigment action, the IDE resolve the functions in synthesis phase and will associate the right function to the operands.

 

[K-J]

Correct, I add that this aspect of VHDL is called OVERLOAD. This is a mechanism which permit to define more functions with the same name, the use of each function is based on the operand check (or "context" as alexan_e as mentioned). Then in VHDL exist more of one function called "<=". For example when "<=" work with two signals operands in a logic expression, it can make a comparison between their values, when it work with a signals but in a cuncurrent statement it perform an assigment action, the IDE resolve the functions in synthesis phase and will associate the right function to the operands.

That's not quite true. <= as the assignment cannot be overridden. No matter what, the assignment will occur as spelled out in the LRM. <= as the 'less than or equal to' function can be overridden as you indicate.

Kevin Jennings

 

[nanostallmann]

That's not quite true. <= as the assignment cannot be overridden. No matter what, the assignment will occur as spelled out in the LRM. <= as the 'less than or equal to' function can be overridden as you indicate.

Kevin Jennings

Thanks for clarification!