need help with source code in verilog!

[theros]

module car_window(clk,clr,data_up,data_down,move_up,move_down,auto_move_up,auto_move_down,stop_move);
//IO ports
input clk,clr,data_up,data_down,stop_move;
output move_up,move_down,auto_move_up,auto_move_down;

wire clk,clr,data_up,data_down,stop_move;
reg [7:0] counts;
reg move_up,move_down,auto_move_up,auto_move_down,break;


initial
begin
break = 1'b0;
counts = 8'b0;
move_up = 1'b0;
move_down = 1'b0;
auto_move_up = 1'b0;
auto_move_down = 1'b0;

end

always @(posedge data_up or posedge data_down)
begin
break=1'b1;
end
always @(posedge clk)
begin
if (data_up==1'b0 | data_down==1'b0)
begin //5
counts=1'b0;
move_up=1'b0;
move_down=1'b0;
end //5
end

always @(posedge clk)
begin
if (stop_move==1'b1 | break==1'b1)
begin
if (move_up==1'b1) move_up=1'b0;
if (move_down==1'b1) move_down=1'b0;
if (auto_move_up==1'b1) auto_move_up=1'b0;
if (auto_move_down==1'b1) auto_move_down=1'b0;
if (break==1'b1) break=1'b0;
end
end

always @(posedge clk)
begin //1
if (data_up==1'b1)
begin //3
counts = counts + 8'b01;
if (counts === 8'b111) auto_move_up = 1'b1;
if (move_up==1'b0) move_up=1'b1;
end //3
else if (data_down==1'b1)
begin//4
counts = counts + 8'b01;
if (counts === 8'b111) auto_move_down = 1'b1;
if (move_down==1'b0) move_down=1'b1;
end//4
end //1
endmodule

im new in HDL-verilog!Can someone help!
i simulate with modelsim and everything is ok!but when i try to synthesize with Leonardo i get the following error
"C:/VERILOG/Examples/Car_windows.v", line 24: Error, More than one untested edge trigger; cannot infer clock for this always statement
Error(s) found in Verilog source."

 

[RegUser_2]

I'm not sure, the initial statement is synthesizable.

 

[verilog]

You're right, reguser_2. Initial statement is not synthesizable. Besides, the code is used for simulation only. There're lot of wrong things. Theros, you have to study how to code to be synthesizable. I read a hardcopy of a book that mentions only synthesizable statement. I don't remember its title...

 

[strut911]

You have two posedge statements in your always block. The only time this can happen is if one of those statements is a reset. Leonardo looked at your code and realized that neither signal was a reset, and so flagged the block as illegal. There is no structure in the FPGA that can trigger off two edges. Remember the basic building blocks in the FPGA...logic gates and flip flops. Flops only have one clock input and a reset.
strut911

 

[skynet]

theros,

I don't think the synthesizer will allow you to assign two signal to an output port.

always @(posedge clk)
begin
if (data_up==1'b0 | data_down==1'b0)
begin //5
counts=1'b0;
move_up=1'b0;
move_down=1'b0; <-- assign to output move_down
end //5
end

always @(posedge clk)
begin
if (stop_move==1'b1 | break==1'b1)
begin
if (move_up==1'b1) move_up=1'b0;
if (move_down==1'b1) move_down=1'b0; <-- assign to output move_down again
if (auto_move_up==1'b1) auto_move_up=1'b0;
if (auto_move_down==1'b1) auto_move_down=1'b0;
if (break==1'b1) break=1'b0;
end
end

I think this is violet the rules, cause you are driving a output with two input directly. Secondly, I do suggest you put every thing into one block which the sensivity list depend on posedge clk, this will solve you problem, or you can use FSM in your design.