Hui2
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Hello guys,
I am facing hard time with filter as shown below. Would you anyone help me with the vcdl code for this?
it should start with
entity FIR is
generic( size : positive :=16; taps : positive := 4 );
port( clk,resetn : in std_logic;
in1 : in std_logic_vector(size-1 downto 0);
out1 : out std_logic_vector(2*size-1 downto 0) );
end FIR;
Thank you a lot,
I am facing hard time with filter as shown below. Would you anyone help me with the vcdl code for this?
it should start with
entity FIR is
generic( size : positive :=16; taps : positive := 4 );
port( clk,resetn : in std_logic;
in1 : in std_logic_vector(size-1 downto 0);
out1 : out std_logic_vector(2*size-1 downto 0) );
end FIR;
Thank you a lot,