Need help with building adaptive PLL design

[newmedia]

Adaptive PLL design

Hello guys,

I’m trying to build a PLL for a high-end microprocessor. This is for my dissertation, and my advisor is not a PLL guy.
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I don’t have to build a really fancy PLL. However, if the PLL can act like Nehalem PLL, it will be great. Here is the URL of Nehalem paper. **broken link removed**

Until now I figured out these requirements.

Input clock frequency: 133MHz
Nominal output clock frequency 2GHz~3GHz
Frequency resolution: 133MHz
PLL generated jitter: 10ps rms
PLL structure: fractional N or Integer N ???
Lock time: ??? cycle.

If you can comment on the previous specification, I will really appreciate it. Also if you see any thesis or disseration on this topic, please let me know.


Other challenge is to design an adaptive PLL which track supply noise voltage. Nehalem used an analog approach, but I want to try a digital approach. Do you have any suggestion for this?

 

[Vamsi Mocherla]

Adaptive PLL design

Post the paper and I can look into it. Tracking the supply noise is not a very big issue. However, you can design a differntial controlled PLL, which has a reasonable supply rejection by theory. You would need it in a noisy environment.

 

[newmedia]

Re: Adaptive PLL design

Hello Vamsi,

Thank you for replying my thread. I attached the paper. The paper does not show not much detailed information, but you can take a look.

Especially Figure 3 is the important one.


The supply noise will be a sinusoidal, and frequency will be 400MHz (Max).